CMOS image sensors can use arrays of 4-transistor (“4T”) pixels. A 4T pixel generally includes a photodiode (i.e., a photo-sensitive element responsible for collecting electromagnetic energy and converting the collected electromagnetic energy into electrons), a transfer transistor, a source follower amplifier transistor, and a row select transistor. Electrons accumulated in the photosensitive region of the photodiode are ultimately converted into a signal voltage by the transistor components of the pixel cell. One type of photodiode common in CMOS image sensors is a pinned photodiode. In particular, a p-n-p pinned photodiode is typically constructed using a p-type semiconductor substrate, an n-type well implanted into the p-type substrate, and a p+ layer implanted into the n-type well. This p+ layer acts as the “pin” in a p-n-p photodiode.
The efficiency with which the photosensitive region of a photodiode converts incident electromagnetic energy into accumulated electrons depends on many factors, including the full well capacity (FWC) of the photodiode. FWC is a measure of the number of electrons a photodiode can store before it reaches saturation. When the saturation of a photodiode is reached, excess electrons may overflow to adjacent pixels. Increased photodiode FWC may result in a higher dynamic range and higher signal-to-noise ratio for a CMOS sensor, which ultimately results in higher-quality digital images.
Recently, CMOS image sensors have been designed for backside illumination (“BSI”). BSI refers to the illumination of the photo-sensitive region of the photodiode on the surface of the exposed semiconductor substrate (i.e., the backside) or, in the case where an additional p+ implant layer is disposed on a silicon p-type substrate, on the side of the p+ implant. In BSI image sensors, illumination occurs without interference from any metal or oxide layers that form, for example, the transistor components of the pixel cell and associated interconnects, allowing incident electromagnetic energy a more direct path through the photodiode. In a front-side illumination (“FSI”) CMOS image sensor, the photo-sensitive region of the photodiode is formed on the side of the substrate closest to the polysilicon, oxide and metal layers such that care must be taken to ensure that the photo-sensitive region of an FSI pixel cell is not covered by polysilicon or metal layers. Therefore, more electromagnetic energy can reach the photodiode in a BSI configuration so as to improve image quality.
As pixel cell size decreases, so does the size of photodiode implants and therefore the size of the photodiode. Smaller photodiode implants may result in a decrease in FWC. A simple way to compensate for the decrease in FWC due to a decrease in photodiode size is to increase the doping concentration in the n-well of the p-n-p photodiode, although one trade-off of increasing n-doping concentration may be an increase in image lag.